cat93c46/56/57/66/86 1k/2k/2k/4k/16k-bit microwire serial eeprom features high speed operation: C 93c56/57/66: 1mhz C 93c46/86: 3mhz low power cmos technology 1.8 to 6.0 volt operation selectable x8 or x16 memory organization self-timed write cycle with auto-clear hardware and software write protection power-up inadvertant write protection 1,000,000 program/erase cycles 100 year data retention commercial, industrial and automotive temperature ranges sequential read (except cat93c46) program enable (pe) pin (cat93c86 only) green package option available 93c46/56/57/66/86 f02 pin configuration dip package (p, l) soic package (j,w) cmos eeprom floating gate technology. the devices are designed to endure 1,000,000 program/erase cycles and have a data retention of 100 years. the devices are available in 8-pin dip, 8-pin soic or 8-pin tssop packages. description the cat93c46/56/57/66/86 are 1k/2k/2k/4k/16k-bit serial eeprom memory devices which are configured as either registers of 16 bits (org pin at v cc ) or 8 bits (org pin at gnd). each register can be written (or read) serially by using the di (or do) pin. the cat93c46/56/ 57/66/86 are manufactured using catalysts advanced soic package (s,v) 93c46/56/57/66/86 f01 pin functions pin name function cs chip select sk clock input di serial data input do serial data output v cc +1.8 to 6.0v power supply gnd ground org memory organization nc no connection pe* program enable block diagram note: when the org pin is connected to vcc, the x16 organiza tion is selected. when it is connected to ground, the x8 pin is selected. if the org pin is left unconnected, then an internal pullup device will select the x16 organization. soic package (k,x) ? 2002 by catalyst semiconductor, inc. characteristics subject to change without notice. tssop package (u,y) *only for 93c86 cs sk di do v cc nc (pe*) org gnd 1 2 3 4 8 7 6 5 cs sk di do v cc org gnd 1 2 3 4 8 7 6 5 v cc cs sk org gnd do di 1 2 3 4 8 7 6 5 cs sk di do v cc org gnd 1 2 3 4 8 7 6 5 nc (pe*) nc (pe*) nc (pe*) 8 7 6 5 v cc org gnd di cs sk do 1 2 3 4 nc (pe*) v cc address decoder memory array organization data register mode decode logic clock generator output buffer do sk cs di org gnd pe* doc. no. 1023, rev. e h a l o g e n f r e e tm l e a d f r e e
2 93c46/56/57/66/86 doc. no. 1023, rev. e absolute maximum ratings* temperature under bias .................. -55 c to +125 c storage temperature ........................ -65 c to +150 c voltage on any pin with respect to ground (1) ............. -2.0v to +v cc +2.0v v cc with respect to ground ................ -2.0v to +7.0v package power dissipation capability (ta = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100 ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. reliability characteristics symbol parameter reference test method min typ max units n end (3) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (3) data retention mil-std-883, test method 1008 100 years v zap (3) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (3)(4) latch-up jedec standard 17 100 ma note: (1) the minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C2.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C1v to v cc +1v. (5) standby current (isb 2 )=0 a (<900na) for 93c46/56/57/66, (isb 2 )=2 a for 93c86. d.c. operating characteristics v cc = +1.8v to +6.0v, unless otherwise specified. symbol parameter test conditions min typ max units i cc1 power supply current f sk = 1mhz 3 ma (operating write) v cc = 5.0v i cc2 power supply current f sk = 1mhz 500 a (operating read) v cc = 5.0v i sb1 power supply current cs = 0v 10 a (standby) (x8 mode) org=gnd i sb2 (5) power supply current cs=0v 0 a (standby) (x16mode) org=float or v cc i li input leakage current v in = 0v to v cc 1 a i lo output leakage current v out = 0v to v cc ,1 a (including org pin) cs = 0v v il1 input low voltage 4.5v v cc <5.5v -0.1 0.8 v v ih1 input high voltage 2 v cc +1 v v il2 input low voltage 1.8v v cc <2.7v 0 v cc x0.2 v v ih2 input high voltage v cc x0.7 v cc +1 v v ol1 output low voltage 4.5v v cc <5.5v 0.4 v v oh1 output high voltage i ol = 2.1ma 2.4 v i oh = -400 a v ol2 output low voltage 1.8v v cc <2.7v 0.2 v v oh2 output high voltage i ol = 1ma v cc -0.2 v i oh = -100 a
3 93c46/56/57/66/86 doc. no. 1023, rev. e pin capacitance symbol test conditions min typ max units c out (3) output capacitance (do) v out =0v 5 pf c in (3) input capacitance (cs, sk, di, org) v in =0v 5 pf note: (1) address bit a8 for 256x8 org and a7 for 128x16 org are "don't care" bits, but must be kept at either a "1" or "0" for read, write and erase commands. (2) applicable only to 93c86 (3) this parameter is tested initially and after a design or process change that affects the parameter. instruction set instruction device start opcode address data comments pe (2) type bit x8 x16 x8 x16 read 93c46 1 10 a6-a0 a5-a0 read address anCa0 93c56 (1) 1 10 a8-a0 a7-a0 93c66 1 10 a8-a0 a7-a0 93c57 1 10 a7-a0 a6-a0 93c86 1 10 a10-a0 a9-a0 x erase 93c46 1 11 a6-a0 a5-a0 clear address anCa0 93c56 (1) 1 11 a8-a0 a7-a0 93c66 1 11 a8-a0 a7-a0 93c57 1 11 a7-a0 a6-a0 93c86 1 11 a10-a0 a9-a0 i write 93c46 1 01 a6-a0 a5-a0 d7-d0 d15-d0 write address anCa0 93c56 (1) 1 01 a8-a0 a7-a0 d7-d0 d15-d0 93c66 1 01 a8-a0 a7-a0 d7-d0 d15-d0 93c57 1 01 a7-a0 a6-a0 d7-d0 d15-d0 93c86 1 01 a10-a0 a9-a0 d7-d0 d15-d0 i ewen 93c46 1 00 11xxxxx 11xxxx write enable 93c56 1 00 11xxxxxxx 11xxxxxx 93c66 1 00 11xxxxxxx 11xxxxxx 93c57 1 00 11xxxxxx 11xxxxx 93c86 1 00 11xxxxxxxxx 11xxxxxxxx x ewds 93c46 1 00 00xxxxx 00xxxx write disable 93c56 1 00 00xxxxxxx 00xxxxxx 93c66 1 00 00xxxxxxx 00xxxxxx 93c57 1 00 00xxxxxx 00xxxxx 93c86 1 00 00xxxxxxxxx 00xxxxxxxx x eral 93c46 1 00 10xxxxx 10xxxx clear all addresses 93c56 1 00 10xxxxxxx 10xxxxxx 93c66 1 00 10xxxxxxx 10xxxxxx 93c57 1 00 10xxxxxx 10xxxxx 93c86 1 00 10xxxxxxxxx 10xxxxxxxx i wral 93c46 1 00 01xxxxx 01xxxx d7-d0 d15-d0 write all addresses 93c56 1 00 01xxxxxxx 01xxxxxx d7-d0 d15-d0 93c66 1 00 01xxxxxxx 01xxxxxx d7-d0 d15-d0 93c57 1 00 01xxxxxx 01xxxxx d7-d0 d15-d0 93c86 1 00 01xxxxxxxxx 01xxxxxxxx d7-d0 d15-d0 i
4 93c46/56/57/66/86 doc. no. 1023, rev. e limits v cc =v cc =v cc = 1.8v-6v* 2.5v-6v 4.5v-5.5v test symbol parameter min max min max min max units conditions t css cs setup time 200 100 50 ns t csh cs hold time 0 0 0 ns v il = 0.45v t dis di setup time 200 100 50 ns v ih = 2.4v t dih di hold time 200 100 50 ns c l = 100pf t pd1 output delay to 1 1 0.5 0.15 sv ol = 0.8v t pd0 output delay to 0 1 0.5 0.15 sv oh = 2.0v t hz (1) output delay to high-z 400 200 100 ns t ew program/erase pulse width 5 5 5 ms t csmin minimum cs low time 1 0.5 0.15 s t skhi minimum sk high time 1 0.5 0.15 s t sklow minimum sk low time 1 0.5 0.15 s t sv output delay to status valid 1 0.5 0.1 sc l = 100pf sk max maximum clock frequency dc 500 dc 1000 dc 3000 khz a.c. characteristics (93c56/57/66) limits v cc =v cc =v cc = 1.8v-6v* 2.5v-6v 4.5v-5.5v test symbol parameter min max min max min max units conditions t css cs setup time 200 100 50 ns t csh cs hold time 0 0 0 ns v il = 0.45v t dis di setup time 400 200 100 ns v ih = 2.4v t dih di hold time 400 200 100 ns c l = 100pf t pd1 output delay to 1 1 0.5 0.25 sv ol = 0.8v t pd0 output delay to 0 1 0.5 0.25 sv oh = 2.0v t hz (1) output delay to high-z 400 200 100 ns t ew program/erase pulse width 10 10 10 ms t csmin minimum cs low time 1 0.5 0.25 s t skhi minimum sk high time 1 0.5 0.25 s t sklow minimum sk low time 1 0.5 0.25 s t sv output delay to status valid 1 0.5 0.25 sc l = 100pf sk max maximum clock frequency dc 250 dc 500 dc 1000 khz * preliminary data for 93c56/57/66 c l = 100pf a.c. characteristics (93c46/86) c l = 100pf note: (1) this parameter is tested initially and after a design or process change that affects the parameter.
5 93c46/56/57/66/86 doc. no. 1023, rev. e device operation the cat93c46/56(57)66/86 is a 1024/2048/4096/ 16,384-bit nonvolatile memory intended for use with industry standard microprocessors. the cat93c46/56/ 57/66/86 can be organized as either registers of 16 bits or 8 bits. when organized as x16, seven 9-bit instruc- tions for 93c46; seven 10-bit instructions for 93c57; seven 11-bit instructions for 93c56 and 93c66; seven 13-bit instructions for 93c86; control the reading, writing and erase operations of the device. when organized as x8, seven 10-bit instructions for 93c46; seven 11-bit instructions for 93c57; seven 12-bit instructions for 93c56 and 93c66: seven 14-bit instructions for 93c86; control the reading, writing and erase operations of the device. the cat93c46/56/57/66/86 operates on a single power supply and will generate on chip, the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. the ready/busy status can be determined after the start of a write operation by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. if necessary, the do pin may be placed back into a high impedance state during chip select by shifting a dummy 1 into the di pin. the do pin will enter the high impedance state on the falling edge of the clock (sk). placing the do pin into the high impedance state is recommended in applica- tions where the di pin and the do pin are to be tied together to form a common di/o pin. figure 1. sychronous data timing 93c46/56/57/66/86 f03 figure 2a. read instruction timing (93c46) 93c46/56/57/66/86 f04 sk di cs do t dis t pd0, t pd1 t csmin t css t dis t dih t skhi t csh valid valid data valid t sklow sk cs di do t cs standby t hz high-z high-z 11 0 a n a nC1 a 0 0 d n d nC1 d 1 d 0 t pd0
6 93c46/56/57/66/86 doc. no. 1023, rev. e the format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93c46)/ /7-bit (93c57)/ 8-bit (93c56 or 93c66)/10-bit (93c86) (an additional bit when organized x8) and for write operations a 16-bit data field (8-bit for x8 organizations). note: this note is applicable only to 93c86. the write, erase, write all and erase all instructions require pe=1. if pe is left floating, 93c86 is in program enabled mode. for write enable and write disable instruction pe=don? care. read upon receiving a read command and an address (clocked into the di pin), the do pin of the cat93c46/ 56/57/66/86 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ) after the initial data word has been shifted out and cs remains asserted with the sk clock continuing to toggle, the cat93c46/56/66/86 will automatically increment to the next address and shift out the next data word in a sequential read mode. as long as cs is continuously asserted and sk continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. in the sequential read mode, only the initial data word is preceeded by a dummy zero bit. all subsequent data words will follow without a dummy zero bit. write after receiving a write command, address and the data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear and data store cycle of the memory location specified in the instruction. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. (note 1.) the ready/busy status of the cat93c46/56/57/66/86 can be determined by selecting the device and polling the do pin. since this device features auto-clear before write, it is not necessary to erase a memory location before it is written into. figure 3. write instruction timing 93c46/56/57/66/86 f05 figure 2b. read instruction timing (93c56/57/66/86) sk cs di do t cs standby high-z high-z 101 a n a n-1 a 0 d n d 0 busy ready status verify t sv t hz t ew sk cs di do high-z 11 0 a n a nC1 a 0 dummy 0 d 15 . . . d 0 or d 7 . . . d 0 1 11 1 111 11111111 address + 1 d 15 . . . d 0 or d 7 . . . d 0 address + 2 d 15 . . . d 0 or d 7 . . . d 0 address + n d 15 . . . or d 7 . . . don't care
7 93c46/56/57/66/86 doc. no. 1023, rev. e erase upon receiving an erase command and address, the cs (chip select) pin must be deasserted for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of the selected memory location. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. (note 1.) the ready/ busy status of the cat93c46/56/57/66/86 can be determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical 1 state. erase/write enable and disable the cat93c46/56/57/66/86 powers up in the write disable state. any writing after power-up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write instruction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all cat93c46/56/57/66/86 write and clear instructions, and will prevent any accidental writing or clearing of the device. data can be read normally from the device regardless of the write enable/disable status. erase all upon receiving an eral command, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. (note 1.) the ready/busy status of the cat93c46/56/57/66/86 can be determined by selecting the device and polling the do pin. once cleared, the contents of all memory bits return to a logical 1 state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. (note 1.) the ready/ busy status of the cat93c46/56/57/66/86 can be determined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. note 1: this note is applicable only to the cat93c46. after the last data bit has been sampled, chip select (cs) must be brought low before the next rising edge of the clock (sk) in order to start the self-timed high voltage cycle. this is important because if the cs is brought low before or after this specific frame window, the addressed location will not be programmed or erased. 93c46/56/57/66/86 f06 figure 4. erase instruction timing sk cs di do standby high-z high-z 1 a n a n-1 busy ready status verify t sv t hz t ew t cs 11 a 0
8 93c46/56/57/66/86 doc. no. 1023, rev. e figure 7. wral instruction timing 93c46/56/57/66/86 f09 figure 5. ewen/ewds instruction timing 93c46/56/57/66/86 f07 figure 6. eral instruction timing 93c46/56/57/66/86 f08 sk cs di standby 10 0 * * enable=11 disable=00 sk cs di do standby t cs high-z high-z 10 1 busy ready status verify t sv t hz t ew 00 status verify sk cs di do standby high-z 10 1 busy ready t sv t hz t ew t cs d n d 0 0 0
9 93c46/56/57/66/86 doc. no. 1023, rev. e ordering information notes: (1) the device used in the above example is a 93c46si-1.8te13 (soic, industrial temperature, 1.8 volt to 6 volt operating volta ge, tape & reel) package p = pdip s = soic (jedec) j = soic (jedec) k = soic (eiaj) u = tssop m= msop** l = pdip (lead free, halogen free) v = soic, jedec (lead free, halogen free) w = soic, jedec (lead free, halogen free) x = soic, eiaj (lead free, halogen free) y = tssop (lead free, halogen free) prefix device # suffix 93c46 s i te13 product number 93c46: 1k 93c56: 2k 93c57: 2k 93c66: 4k 93c86: 16k tape & reel te13: 2000/reel -1.8 cat temperature range blank = commercial (0? - 70?c) i = industrial (-40? - 85?c) a = automotive (-40? - 105?c) operating voltage blank (v cc =2.5 to 6.0v) 1.8 (v cc =1.8 to 6.0v) optional company id e = extended (-40?c to + 125?c)
copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the company s corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com publication #: 1023 revison: e issue date: 09/23/02 type: final
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